This invention relates to digital delay lines and in particular to a programmable synchronous digital delay line that is adapted to delay, delay and compress, or delay and stretch digital data pulses.
There currently exists the need for a digital delay device that will accurately delay digital data to accomplish synchronization of devices or compensation of timing (propagation) delays through digital equipment.
An example of such a need is found in the VLF/LF communications area. Specifically, there is a requirement in a U.S. Air Force prototype where new digital modems for the Air Force 487L system require the use of this type of device to supply an Antenna Tuning unit with digital data which is synchronized to the RF power applied to the antenna itself. In order to precisely synchronize the digital data to the RF output slewing waveform at the system Voltage Controlled Oscillator (VCO), it is mandatory that both the leading and trailing edges (which represent frequency changes) of the digital data be independently controllable. In this system a modulator provides the mark (leading edge) and space (trailing edge) pulses required to allow an automatic antenna tuning device to switch frequencies as the transmitter power output passes through zero. Retuning the antenna at the zero cross over points reduces voltage standoffs and reflected powers to tolerable levels. However, the characteristics of the modulator are such that the slew time from mark to space frequency is not necessarily the same as from space to mark frequency and therefore must be treated separately in two independent digital delay channels. Further, there is a finite time required for the automatic antenna timing device to change frequency once it has received the signal to do so.
Separate processing of mark and space pulse trains to an acceptable degree of accuracy, however, is not readily accomplished with state of the art digital delay techniques. In order to achieve acceptably high accuracy using currently available delay devices a very high clock rate would be necessary requiring an extremely long shift register running very fast. Furthermore, separate processing of mark and space pulse trains with currently available digital devices requires two sets of digital delay circuits together with a switching matrix, making the system very complex and prohibitively expensive in many instances.
The present invention solves these problems by providing a programmable synchronous digital delay that allows independent control of the leading and trailing edges of the data pulses with simplified digital circuits thereby obtaining large delays together with data pulse leading and trailing edge control using minimum hardware.